csmc provide accurate and validated pdks to our mutual customers for fast time-to-market by maximizing design productivity. these process packages consist of all the necessary components to design, simulate, layout, and verify a chip design, including schematic symbols, device models, technology files, parameterized cells (pcells), physical verification decks(drc/lvs/lpe), etc.
| packaged design documents | pdh(process design handbook) | process outline | |
|---|---|---|---|
| application note | |||
| layout rule | |||
| electrical design rule | |||
| pcm spedfication | |||
| mask tooling table | |||
| spice model | |||
| esd protection design guideline | |||
| characteristics report | |||
| command files | calibre | drc | |
| lvs/xrc/mipt | |||
| qrc | xrc | ||
| std.cell library&io memory compiler | |||
| pdk | |||